Zinc phosphorus nitride-oxide wide-bandgap gate and interlayer dielectric

Zn4P6N12O is a quaternary zinc phosphorus nitride-oxide that sits precisely on the thermodynamic convex hull — meaning it is not merely a plausible candidate but a genuinely stable phase with zero calculated energy above hull — and carries a computed bandgap of approximately 2.97 eV at the PBE level. That combination makes it a computed candidate, subject to a hybrid-functional gap calculation, for the wide-bandgap dielectric applications sought as the industry moves beyond silicon dioxide and into gate stacks and interlayer dielectrics that must tolerate higher voltages, wider operating temperatures, and increasingly aggressive scaling. The material was identified through computational graph-guided discovery, and a preliminary claim-level screen across more than 300,000 materials patents found no prior patent claim blocking its use in dielectric device applications; this is not a freedom-to-operate opinion. The timing matters because the semiconductor industry is navigating a forced substitution event. Hafnium oxide and aluminum oxide — the two entrenched high-k dielectric workhorses — are running into physical and integration limits as gate lengths shrink below five nanometers and as advanced packaging architectures impose new thermal and electrical demands on interlayer and package-substrate dielectrics. Wide-bandgap materials are essential for leakage suppression and breakdown-voltage headroom, but the candidate space that has been experimentally explored is narrow and heavily patented. Zn4P6N12O opens a fresh compositional vein: the nitride-oxide class has been studied only sparsely in the patent literature, and this specific stoichiometry appears to occupy genuine whitespace. The asset is the lead claim of Family 15 within the dielectric, ferroelectric, and wide-bandgap oxides portfolio, and it is structured as a composition-plus-device-use claim covering gate dielectric, interlayer dielectric, passivation, and package-substrate dielectric applications simultaneously. For a buyer evaluating the dielectric portfolio, this asset represents an opportunity to establish proprietary composition rights over a thermodynamically grounded, computationally validated wide-bandgap nitride-oxide at the exact moment when the industry is actively searching for alternatives to incumbents. The preliminary screen (not a freedom-to-operate opinion) and the computed on-hull placement give early indications on two of the biggest early-stage risks: freedom to practice and synthesizability in principle.

Candidates are screened for imaginary phonon modes with the machine-learning interatomic potentials named above. This is a computed harmonic check, not a measurement; where engines disagree, that is shown.

Zn4P6N12O is a quaternary compound containing zinc, phosphorus, nitrogen, and oxygen in a 4:6:12:1 atomic ratio. The nitride-oxide family it belongs to — materials that combine nitrogen and oxygen as mixed anion species around a metal or metalloid cation framework — is a structurally rich but experimentally underexplored class. The mixed-anion character is precisely what creates the chemical versatility: nitrogen's lower electronegativity and different bonding geometry relative to oxygen allow the crystal to adopt coordination environments unavailable to pure oxides, which can tune the dielectric response and bandgap in ways that single-anion systems cannot. The phosphorus in this composition acts as a network-former, analogous to its role in phosphate glasses, contributing to the rigidity and thermodynamic stability of the framework. The computed PBE bandgap of approximately 2.97 eV places the material at the boundary between conventional semiconductors and the wide-bandgap regime, and HSE-level correction — which systematically opens PBE gaps in materials of this type — is expected to push the gap above 3 eV; gate dielectrics generally need much wider gaps and adequate band offsets to silicon, so gate-dielectric candidacy awaits hybrid gap and offset calculations. The HSE calculation remains an open validation gate. The thermodynamic stability assessment is unusually robust for an early-stage computational candidate. The material was placed on the convex hull — energy above hull measured at approximately zero millielectronvolts per atom — meaning that within the Zn-P-N-O chemical space, Zn4P6N12O is predicted to be among the most stable phases accessible, not merely a local minimum. Critically, dynamic (phonon) stability was evaluated not by a single potential but by four independent machine-learning interatomic potentials: MACE, CHGNet, MatterSim, and ORB. All four returned a stable verdict — no imaginary phonon modes were found — which means the consensus is unanimous across frameworks trained on entirely different datasets and with different architectural biases. This four-of-four agreement is a much stronger signal than any single-potential result, because each potential has its own systematic errors and a coincidental false positive across all four is highly unlikely. The space group of the lowest-energy polymorph was not resolved in the current dataset and remains to be determined by structure refinement, but the convex-hull placement is referenced to that lowest-energy structure. The simulation chain performed to date covers two essential layers. First, the convex-hull placement through DFT establishes thermodynamic ground truth for the composition. Second, the four-engine phonon consensus (no imaginary modes) shows the structure is a local potential-energy minimum, i.e. dynamically stable — a prerequisite, not a guarantee, for a material that must survive thin-film deposition and device operation; decomposition into competing phases is a separate hull and kinetics question. What the chain does not yet cover, and what would need to be completed before a licensing conversation with a process-integration team, are the dielectric tensor components. A DFPT calculation delivering both the total dielectric constant (epsilon-total, which governs capacitance in a gate stack) and the electronic contribution (epsilon-infinity, which sets the optical response) is listed as an open proof gate. These numbers would quantify the dielectric benefit relative to HfO2 and Al2O3 and give a process engineer a concrete figure of merit. The material has one DFT source in the current record, which is appropriate for an early-stage lead that has been validated at the stability-screening level but has not yet been subjected to property-specific higher-level calculations. The preliminary FTO screen, combined with the on-hull stability and the four-potential consensus, makes this one of the stronger early-stage claims in the portfolio from a risk-adjusted standpoint, even with the dielectric tensor and HSE gap still outstanding.

The addressable market for gate and interlayer dielectric materials in advanced logic and memory is large and structurally resilient. Gate dielectrics are consumed in every advanced logic node — every CMOS transistor in every chip requires a gate stack — and the interlayer dielectric market spans the full stack of backend-of-line wiring levels in logic, DRAM, and NAND. Advanced packaging adds a third consumption channel: package-substrate dielectrics and passivation layers for chiplet-based architectures (2.5D and 3D integration) that are growing rapidly as the industry shifts from monolithic scaling to heterogeneous integration. The combined addressable market for dielectric materials serving these three applications is estimated in the range of one to five billion dollars, though this is a preliminary sizing estimate based on industry-level data and the actual capturable market for any single composition will depend on adoption rate and process integration costs. Who buys in this market is important to understand. The primary customers are not consumers but process engineers and materials procurement functions at integrated device manufacturers (IDMs) and foundries — Intel, TSMC, Samsung, GlobalFoundries, and their tier-one equipment and precursor suppliers. These buyers license or acquire composition rights because they need freedom to develop new deposition chemistries (ALD, CVD) around a novel dielectric without infringing a third-party composition patent. A foundry that wants to qualify a new high-k dielectric must have either a license or ownership of any blocking composition claim. The secondary buyer channel is the specialty chemical and precursor industry: companies like Air Liquide, Entegris, Merck KGaA, and Versum that develop and sell ALD precursors would need a composition license if the target film is covered by a granted patent. Royalty and licensing logic in this space typically follows one of two models. For a composition-plus-device-use patent covering a specific stoichiometry in gate dielectric applications, a foundry or IDM might take a paid-up license at the time of process qualification, with the lump sum reflecting the expected node lifetime and wafer volume. Alternatively, a running royalty can be structured as a per-wafer fee applied to production nodes using the material. Because the claim covers not just one application but four — gate dielectric, interlayer dielectric, passivation, and package-substrate dielectric — the licensing surface is broad, and a single patent can generate multiple independent revenue streams from the same composition.

on-hull 4-engine-stable exact wide-bandgap dielectric with a preliminary FTO screen whitespace

wide-bandgap dielectric device-use; CLEAN on Track-B claim-level prescreen

Preliminary screen only. This is not a freedom-to-operate opinion.

The most natural strategic buyers for this asset are advanced logic foundries and IDMs that are actively qualifying next-generation gate dielectric and interlayer dielectric materials for sub-five-nanometer nodes and for chiplet-based advanced packaging architectures. TSMC, Samsung Foundry, Intel Foundry, and GlobalFoundries all have active advanced dielectric programs and would benefit from securing composition rights over a thermodynamically stable, preliminary-FTO-screened wide-bandgap nitride-oxide before a competitor does. The asset is also relevant to specialty ALD precursor and process chemistry suppliers — Entegris, Merck KGaA, Air Liquide Advanced Materials, and Versum — who develop deposition chemistries around licensed composition claims and who would find value in an exclusive or field-of-use license tied to a specific device application (for example, exclusive rights for gate dielectric use while licensing interlayer dielectric use separately). A second buyer category is the advanced packaging ecosystem: substrate manufacturers (Ibiden, Shinko, AT&S) and packaging houses (Amkor, ASE, JCET) that are developing new dielectric materials for redistribution layers and passivation in 2.5D and 3D packages. The package-substrate dielectric application included in the claim is directly relevant to this buyer segment, which is growing faster than traditional node-level semiconductor markets and where the patent landscape for novel dielectrics is thinner and easier to enter. For either buyer category, the asset is best positioned as a license-and-develop transaction rather than a direct product sale, given the current stage of computational validation.

The primary technical risk is that the outstanding proof gates — HSE bandgap and DFPT dielectric tensor — return values that undercut the wide-bandgap and high-k claims. If the HSE gap comes in at or below 3 eV, the "wide-bandgap" characterization in the claims may require narrowing or re-framing, and if the dielectric constant is low (below that of SiO2 at 3.9, or only marginally above it), the commercial case for the material relative to incumbents weakens significantly. The mitigation is straightforward: these calculations should be completed before, not after, any licensing conversation. The space group of the lowest-energy polymorph has also not been resolved, which creates a mild prosecution risk if a different research group independently identifies and claims the same composition in a characterized crystal structure before the non-provisional is filed; resolving the structure by refinement or higher-level DFT is therefore advisable before filing. On the commercial side, the principal risk is the long qualification timeline for any new dielectric material in a production semiconductor process — even a material with excellent computed properties typically requires two to four years of experimental deposition development, interface characterization, and reliability testing before it can influence a production process flow, which means licensing revenue is back-weighted and dependent on a buyer's development commitment. The preliminary FTO screen and on-hull thermodynamic stability reduce two of the largest early-stage risks and leave the path to value creation well-defined, if not short.