Aluminum nitride thermal liner for through-glass vias in advanced packaging

Through-glass vias are the thermal weak link in glass-core advanced packaging. Glass is a poor thermal conductor, and the conventional TaN/TiN diffusion barriers that line via walls add zero thermal function — they block copper migration and nothing else. This asset changes that geometry: a conformal wurtzite aluminum nitride liner deposited between the glass via wall and the copper barrier converts the via itself into a functioning heat path. On a one-dimensional series-resistance model, the liner cuts through-via thermal resistance by 50% or more. The novelty is not the existence of AlN as a material — it is a well-characterized, fab-friendly nitride with decades of substrate use. The novelty is the ordered placement: AlN on the via wall, inside an integrated through-glass via stack, in a configuration the prior art around standalone AlN substrates does not occupy. That distinction is both the basis of patentability and the basis of clean freedom-to-operate. The timing is specific. Glass-core substrates are entering high-volume HBM4 and AI accelerator packaging now, and thermal dissipation through the via array is already the binding constraint limiting stack height and power density. Incumbent barrier suppliers cannot address this constraint without changing their entire chemistry. A buyer who secures this position enters the glass-core thermal stack at the right moment, before the architecture becomes locked in.

Each candidate is validated by multiple independent machine-learning interatomic potentials. A material advances only when the engines agree on phonon (dynamic) stability — disagreement is surfaced, not hidden.

The liner material is wurtzite aluminum nitride, space group P6_3mc, with a wide bandgap of 6.0 eV. That bandgap is why the liner works electrically: AlN is a robust electrical insulator, so it can occupy the via wall between glass and copper without introducing leakage paths. At the same time, AlN is among the highest-thermal-conductivity materials available at moderate deposition temperatures. The internal anharmonic calculation — a Phono3py run on a 12x12x12 supercell using force constants from a MACE-MP-0 phonon calculation — yields a bulk thermal conductivity of approximately 265 W/m/K. That is a best-case, bulk-crystal figure. Realistic thin-film values on a via wall, where grain boundaries, stress, and deposition conditions attenuate transport, fall in the 18 to 50 W/m/K range. Both numbers are reported candidly, because the 18 to 50 W/m/K range is the operationally relevant one. Even at the lower end, thin-film AlN carries roughly 1 to 10 times the thermal conductivity of thin-film alumina, which is the only competing electrically-insulating dielectric option for this position in the stack. Phonon stability has been independently confirmed by two machine-learning interatomic potentials. MACE returned a minimum phonon frequency of +1.34 THz; CHGNet returned +0.385 THz. Both potentials agree that the wurtzite structure is dynamically stable — there are no imaginary phonon modes under either calculation. Three independent DFT literature sources corroborate the structural data. The calculation stack is therefore three-layer: published DFT reference data, cross-validated by two independent ML potentials, anchored by an anharmonic thermal conductivity simulation. For a material with extensive published deposition recipes across sputtering, ALD, PEALD, and CVD, that computational stack is well above the bar for advancing to thin-film coupon fabrication. The thermal-resistance improvement arises directly from the series-resistance physics of the via stack. Bare glass plus barrier is a high-resistance thermal series path. Inserting a 18-to-50 W/m/K liner between glass and barrier adds a parallel conduction channel along and across the via wall, reducing the total series resistance. The one-dimensional model projects a reduction of 50% or more. The geometry of ALD or PEALD deposition makes conformal coverage of high-aspect-ratio via walls achievable with existing semiconductor tooling, which is a significant process-integration advantage over materials that require exotic deposition methods.

The addressable market is advanced semiconductor packaging for high-bandwidth memory and AI accelerator applications, currently estimated at over $10 billion and growing as HBM4, HBM5, and next-generation AI accelerator tiles push toward glass-core substrates at volume. The buyers are HBM manufacturers, AI accelerator-focused OSATs, and glass-core substrate vendors — three distinct tiers that all face the same thermal constraint in the via array. The commercially relevant slice of that market is the thermal-management and via-liner process step within glass-core substrate manufacturing. Substrates that incorporate a thermal liner command a process adder; the value proposition is headroom for higher stack heights and greater power density, both of which directly translate to product performance differentiation at the HBM and accelerator level. A per-wafer or per-panel running royalty on glass-core substrates incorporating the liner is the natural licensing structure, because the liner is a thin process module inserted into an existing barrier-ALD flow — it does not require a new tool set, just a recipe change and a qualification run. Value capture scales with substrate area and stack height, which makes the royalty base grow naturally as the industry moves to larger panel formats and taller HBM stacks. No committed customer pricing exists at this stage; the figures above are market estimates based on publicly reported advanced-packaging segment sizes. The decisive qualification event is a measured thin-film kappa on an actual via-wall coupon, which is the next funded step and the event that converts the thermal advantage from modeled to demonstrated for design-win conversations.

~1-10x thin-film kappa vs thin-film alumina; addresses the binding thermal constraint barriers cannot

TGV-integrated config; standalone AlN substrate panels excluded

The most motivated acquirers are HBM manufacturers and the hyperscaler-linked AI accelerator integrators who specify the substrate stack. For these buyers, thermal headroom in the via array directly limits memory bandwidth density and power envelope — the core product metrics for HBM4 and beyond. Acquiring or exclusively licensing the thermal-liner position before a competitor does creates a differentiation lock-in that persists for the duration of the glass-core platform's product cycle, which is likely three to five years given the qualification timelines in advanced packaging. OSATs and glass-core substrate vendors are the natural field-of-use licensees. They integrate the liner as a process module into barrier-ALD flows on behalf of their HBM and accelerator customers, and a running royalty on substrate area is the straightforward commercial structure. The most valuable deal structure for a seller is an exclusive license or outright acquisition to one HBM or accelerator strategic for the high-performance-compute field of use, with non-exclusive licenses to substrate vendors and OSATs for remaining fields. Exclusivity commands a premium specifically because the liner occupies the thermal critical path of the flagship packaging architecture at the moment the architecture is being locked in — that window is narrow and the leverage is highest now.

Two risks are real and should be stated directly. First, the thermal resistance reduction of 50% or more rests on a one-dimensional series-resistance model using thin-film kappa values that have not yet been measured on actual via-wall geometry. The bulk anharmonic figure of 265 W/m/K is substantially higher than the 18 to 50 W/m/K range used in the model, and even the modeled range is an estimate until a TDTR or 3-omega measurement on a via-wall coupon confirms it. If thin-film kappa on this geometry falls toward the lower end of the range or below it, the percentage improvement shrinks. Second, conformality, adhesion, and residual stress of an AlN liner inside high-aspect-ratio through-glass vias — and its mechanical and chemical compatibility with the copper barrier deposited on top — remain to be demonstrated at production-relevant via dimensions and aspect ratios. The claim strategy also carries a scope risk: the configuration-novelty basis requires the claim to read clearly on the integrated stack while staying outside the dense standalone-substrate prior art. That line is well-drawn in the current claim set and is reinforced by explicit negative limitations, but it will be tested during examination and in any enforcement proceeding. The decisive de-risking step for all three concerns is the same: fabricate a test coupon — a via-wall AlN thin film at representative thickness and aspect ratio — and measure thermal conductivity, conformality, and adhesion. That single experiment answers the measurement question, validates the process integration assumptions, and provides data to anchor claim scope arguments during prosecution.